This invention relates to a multilayer interconnection structure, and more particularly to a multilayer interconnection structure using a blanket W (tungsten) plug and a method for manufacturing the same.
As the size of elements is reduced, inter-connection layers for connecting the elements tend to be further miniaturized and more frequently formed into a multilayered form and this tendency is considered to persist also in the future. At present, it is required to set up the interconnecting technique of stable characteristic and high reliability capable of coping with the above tendency.
The conventional interconnection is explained below with reference to the accompanying drawings by taking a two-layered interconnection structure as an example. A semiconductor substrate having elements formed therein is disposed below the interconnection structure, but it is omitted in the drawing.
FIG. 9 is a schematic cross sectional view showing a conventional semiconductor device. In the conventional semiconductor device shown in FIG. 9, an inter-level insulating film 92 is formed on a first Al (aluminum) film 91a used as a lower interconnection layer and a contact hole 92a is formed in the inter-level insulating film 92 to partly expose the first Al film 91a. On the internal side surface of the contact hole 92a and part of the first Al film 91a corresponding to the bottom surface of the contact hole, a first TiN (titanium nitride) film 93 is formed and a W film 94 is formed to fill the contact hole 92a and form a plug. A second TiN film 95 is formed on the plug and an upper interconnection layer formed of a second Al film 91b is formed on the second TiN film 95.
Next, a method for manufacturing the semiconductor device of FIG. 9 is explained. FIGS. 10 to 14A, 14B show the manufacturing process for the conventional semiconductor device.
(1) As shown in FIG. 10, a first Al film 91a is formed on a semiconductor substrate (not shown). An inter-level insulating film 92 such as a CVD-SiO.sub.2 film is formed on the surface of the first Al film 91a. The inter-level insulating film 92 is patterned into a preset shape by the RIE (reactive ion etching) technique to form a contact hole 92a therein to expose part of the surface of the first Al film 91a.
(2) As shown in FIG. 11, a first TiN film 93 is formed as a grow layer on the inter-level insulating film 92, the internal side surface of the contact hole and the first Al film 91a exposed in the contact hole by DC magnetron sputtering and then a W film 94 is formed on the first TiN film 93 by the CVD method. The film thickness of the first TiN film 93 is approx. 100 nm and the film thickness of the W film 94 is approx. 400 nm.
(3) Next, as shown in FIG. 12, after the planarization process by RIE using F-(fluorine)-series or O-(oxygen)-series gas is effected, the W film 94 and first TiN film 93 formed in a portion higher than the surface level of the inter-level insulating film 92 are removed by etching so as to form a plug PL in the contact hole.
(4) Then, as shown in FIG. 13, after a second TiN film 95 is formed on the inter-level insulating film 92, W film 94 and first TiN film 93 by DC magnetron sputtering, a second Al film 91b is formed on the second TiN film 95. The film thickness of the second TiN film 95 is approx. 50 nm and the film thickness of the second Al film 91b is approx. 800 nm.
(5) Next, a resist 96 is formed to a thickness of approx. 2.0 .mu.m on the entire surface of the resultant structure, and then, as shown in FIG. 14A, the resist 96 is patterned by the lithography technology. The second Al film 91b and second TiN film 95 are etched by RIE using Cl-(chlorine)-series gas with the patterned resist used as a mask to form an upper interconnection layer as shown in FIG. 14B.
In the step (2), formation of the first TiN film 93 as the grow layer in the contact hole is indispensable for uniformly growing the W film by the CVD method.
As the size of elements is reduced, the width of a mask used for forming the upper interconnection layer 91b is extremely reduced and is made substantially equal to the width of the contact hole. As a result, the position of the resist 96 used for patterning the second Al film 91b and the second TiN film 95 is deviated from the upper position of the contact hole in some cases as shown in FIG. 15A.
After a wafer is set in the RIE device as in the normal way in this state, an etching gas is supplied to effect the RIE process, but in this case, since the distribution of the etching gas is non-uniform on the plane of the wafer, a variation occurs in the etching rate. As is well known in the art, if the second Al film 91b and the second TiN film 95 other than the interconnection layer portion are left behind on the inter-level insulating layer 92, the electrical characteristic of the element will be made defective. Therefore, variations in the film thicknesses of the second Al film 91b and the second TiN film 95 are taken into consideration and the etching process is effected until the second TiN film 95 can be patterned without fail in a region in which the etching rate is low.
In the RIE process using Cl-series gas, since the etching rate is slow for the W film in comparison with the etching rate for TiN, the first TiN film 93 is etched in a region in which the mask is not disposed. That is, since over-etching is effected to stably pattern the interconnection layer, the first TiN film 93 which covers the internal side surface of the contact hole and which is not usually removed is etched out as shown in FIG. 15B to provide a narrow space 93a. Since it is difficult to form an insulating film which is formed in the next step in the narrow space 93a, a void occurs in the narrow space 93a, thereby lowering the service life and reliability of the interconnection layer.